This invention relates to performing computations having multiple input values using the logic elements of a programmable logic device, and, more particularly, to decomposing a large computation into sub-computations and performing the sub-computations using the carry chain logic of the logic elements.
Programmable logic devices have played and continue to play an important role in today's electronic devices and applications. The programmable logic device (PLD) bridges the spectrum between hardwired electronics on one end and fully programmable processor-based platforms on the other end. A PLD provides the benefits of both ends of the spectrum in that it provides more flexibility than a hardwired device and performs programmed operations without the complex architectural requirements of a processor-based system. Accordingly, there continues to be great interest in programmable logic devices.
In particular, computation delay in PLDs continues to be a topic of great interest. In computing architectures that use programmable logic and routing, the programming flexibility comes at the cost of slower computation speed. Some advances in PLD technology have been directed to improving the computation speed of particular types of operations. For example, U.S. Pat. No. 5,274,581 to Cliff et al., which is hereby incorporated herein by reference in its entirety, describes an improved PLD technology for quickly computing and communicating carry information for addition and counter operations. Using this technology, multiple PLD logic elements can be coupled together by their carry connections to allow carry information to quickly propagate from one logic element to another. This type of architecture is known as a “carry chain.”
The concepts employed in a carry chain are also applicable to computations other than addition or counter operations. Since many computations are significantly more complicated and time consuming than addition or counter operations, there is interest in adapting carry chain concepts to performing general computations in a programmable logic device.